Abstract
Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmable gate array (FPGA) based reconfigurable coprocessor board (the Chameleon Coprocessor) being used to evaluate hardware architectures for speedup of array computation algorithms. These algorithms have been developed using a Mathematics of Arrays (MOA) and are optimal in the sense that they reduce normal array cartesian indexing operations to a series of primitive additions and offsets based on array shape. The method is simple yet powerful, produces algorithms which are provably correct, and are independent of dimensionality. Software implementations have been used to provide speedups on the order of 100% to the solution of heat transfer equations on a uniprocessor. We extend these methods to application designs for the Chameleon Coprocessor.
Recommended Citation
Pottinger, H.; Eatherton, W.; Schiefelbein, T.; Mullin, L.; and Ziegler, R., "An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays" (1994). Computer Science Technical Reports. 174.
https://scholarsmine.mst.edu/comsci_techreports/174
Department(s)
Computer Science
Second Department
Electrical and Computer Engineering
Report Number
CSc-94-25
Document Type
Technical Report
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 1994 University of Missouri - Rolla, All rights reserved
Publication Date
1 June, 1994
Comments
The second, third and fifth Authors are Graduate Students.