Abstract
Work in progress at the University of Missouri - Rolla on hardware assists for high performance computing and communication is presented. This research consists of a field programmable gate array based rapid prototyping environment (Chameleon) being used to evaluate hardware architectures for speedup of array partitioning and routing algorithms. These algorithms have been developed using a Mathematics of Arrays (MOA) and are optimal in the sense that they reduce normal array indexing operations to a series of primitive additions based on array shape. The method is simple yet powerful, produces algorithms which are provably correct, and are independent of dimensionality. Software implementations have been used to provide speedups on the order of 100 % to the solution of heat transfer equations on a uniprocessor.
Recommended Citation
Pottinger, H.; Eatherton, W.; Mullin, L.; and Schiefelbein, T., "Hardware Assists for High Performance Computing using a Mathematics of Arrays" (1994). Computer Science Technical Reports. 173.
https://scholarsmine.mst.edu/comsci_techreports/173
Department(s)
Computer Science
Second Department
Electrical and Computer Engineering
Report Number
CSc-94-24
Document Type
Technical Report
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 1994 University of Missouri - Rolla, All rights reserved
Publication Date
1 June, 1994
Comments
The second and fourth Authors are Graduate Students.