Title

FPQSC: FPGA-Based Parallel Quasi-Stochastic Computing

Presenter Information

Joseph Drury

Department

Electrical and Computer Engineering

Major

Computer Engineering

Research Advisor

Choi, Minsu

Advisor's Department

Electrical and Computer Engineering

Funding Source

National Science Foundation (U.S.)

Abstract

Integrated circuit scaling creates vulnerabilities in digital circuits; increasing errors make designs unreliable. Ultra-small and low-power designs are necessary but increasingly complex, solutions become highly sophisticated. Stochastic computation (SC) is a re-emerging technique used to deal with small, low-power circuitry. SC has proven advantageous for image processing and neural networks, but implementation has been hindered because random fluctuations in stochastic numbers cause exponentially increasing run times. Application of pseudo-random number generators (PRNG) tend to generate sequences with un-equilateral bit spacing. To mitigate this issue, implemented look-up tables (LUT) create stochastic number generators, influenced by quasi-random number sequences. The proposed design, stochastic bit matrix processing (SBM), was implemented on a Virtex-4 FPGA board to calculate probability values using the value of clock cycles ran. Parallel application of SNG was implemented using LUT, increasing throughput and decreasing execution time. Applying SBM to edge detection achieves better results than PRNG as SNGs.

Biography

Joseph is an undergraduate student studying Computer Engineering in the Electrical and Computer Engineering Department. He is a member of IEEE, Eta Kappa Nu, and Tau Beta Pi. He looks forward to a co-op with Nucor-Yamato Steel and will pursue a Masters Degree in Computer Engineering.

Research Category

Engineering

Presentation Type

Oral Presentation

Document Type

Presentation

Location

Turner Room

Presentation Date

11 Apr 2016, 10:20 am - 10:40 am

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Apr 11th, 10:20 AM Apr 11th, 10:40 AM

FPQSC: FPGA-Based Parallel Quasi-Stochastic Computing

Turner Room

Integrated circuit scaling creates vulnerabilities in digital circuits; increasing errors make designs unreliable. Ultra-small and low-power designs are necessary but increasingly complex, solutions become highly sophisticated. Stochastic computation (SC) is a re-emerging technique used to deal with small, low-power circuitry. SC has proven advantageous for image processing and neural networks, but implementation has been hindered because random fluctuations in stochastic numbers cause exponentially increasing run times. Application of pseudo-random number generators (PRNG) tend to generate sequences with un-equilateral bit spacing. To mitigate this issue, implemented look-up tables (LUT) create stochastic number generators, influenced by quasi-random number sequences. The proposed design, stochastic bit matrix processing (SBM), was implemented on a Virtex-4 FPGA board to calculate probability values using the value of clock cycles ran. Parallel application of SNG was implemented using LUT, increasing throughput and decreasing execution time. Applying SBM to edge detection achieves better results than PRNG as SNGs.