Title

Area & Latency Measurement and Optimization of Clock-Free Nanowire Reconfigurable Crossbar

Presenter Information

Jeffrey Ahrendts

Department

Electrical and Computer Engineering

Major

Computer Engineering

Research Advisor

Choi, Minsu

Advisor's Department

Electrical and Computer Engineering

Funding Source

NSF ECCS - 0801362

Abstract

This research project involves the study of Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) to develop a more efficient and practical way of implementing this form of nanotechnology. This architectures design that is based on Null Convention Logic (NCL), a delayed insensitive logic that is not dependent on a global clocking distribution network. By using this logic, faults encountered with regular clocking networks can be avoided. By optimizing the newly crossbar system a newly hierarchical design was created to be build more complex logic blocks. From this proposed measurements and optimization methods can be used to estimate area and latency for different blocks. In this experiments, these logic blocks are configured to implement the structure of full adders to support the design effectiveness.

Biography

Jeffrey Ahrendts is a dual-degree engineering transfer student from Morehouse College who's hometown is Sunrise, FL. He is currently a senior here at Missouri S&T pursing a B.S. of Computer Engineering and B.S. of General Science with Mathematics and Japanese minor from Morehouse College.

Research Category

Engineering

Presentation Type

Oral Presentation

Document Type

Presentation

Award

Engineering oral presentation, Third place

Location

Ozark Room

Presentation Date

07 Apr 2010, 10:00 am - 10:30 am

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Apr 7th, 10:00 AM Apr 7th, 10:30 AM

Area & Latency Measurement and Optimization of Clock-Free Nanowire Reconfigurable Crossbar

Ozark Room

This research project involves the study of Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) to develop a more efficient and practical way of implementing this form of nanotechnology. This architectures design that is based on Null Convention Logic (NCL), a delayed insensitive logic that is not dependent on a global clocking distribution network. By using this logic, faults encountered with regular clocking networks can be avoided. By optimizing the newly crossbar system a newly hierarchical design was created to be build more complex logic blocks. From this proposed measurements and optimization methods can be used to estimate area and latency for different blocks. In this experiments, these logic blocks are configured to implement the structure of full adders to support the design effectiveness.