An asynchronous FPGA for NULL Convention Logic circuits
Keywords and Phrases
NULL Convention Logic circuits; Look-up tables
"This Master's thesis is intended to familiarize the reader with the asynchronous delay-insensitive NULL convention Logic (NCL) paradigm and illustrate the design of a completely asynchronous Field Programmable Gate Array (FPGA) for NULL Convention Logic circuits. Mentor Graphics Design Automation tools such as Design Architect and Accusim II were extensively used in creating this design"--Introduction, page 1.
Electrical and Computer Engineering
M.S. in Computer Engineering
University of Missouri--Rolla
ix, 77 pages
© 2005 Arun Balasubramanian, All rights reserved.
Thesis - Citation
Field programmable gate arrays -- Design and construction
Logic circuits -- Design and construction
Print OCLC #
Link to Catalog Record
Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.http://merlin.lib.umsystem.edu/record=b5478770~S5
Balasubramanian, Arun Swaminathan, "An asynchronous FPGA for NULL Convention Logic circuits" (2005). Masters Theses. 3745.
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