The Design of a Lumped Element Impedance-Matching Network with Reduced Parasitic Effects Obtained From Numerical Modeling

Shaofeng Luan
Jun Fan, Missouri University of Science and Technology
James L. Knighten
Norman W. Smith

This document has been relocated to

There were 79 downloads as of 22 Jun 2016.


This paper presents an impedance-matching network design with numerical modeling of the parasitic effects. A modeling tool CEMPIE (a Circuit Extraction approach based on a Mixed Potential Integral Equation formulation) is used to model the hoard-level parasitics of surface mount technology (SMT) resistors for impedance-matching networks. A 3-layer design of impedance-matching network with 0402 SMT resistors is implemented according to the modeling results. And its performance is demonstrated.