Leakage Minimization Technique for Nanoscale CMOS VLSI

Kyung Ki Kim
Yong-Bin Kim
Minsu Choi, Missouri University of Science and Technology
Nohpill Park

This document has been relocated to http://scholarsmine.mst.edu/ele_comeng_facwork/728

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Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents.