The PCB Level ESD Immunity Study by Using 3 Dimension ESD Scan System

Kai Wang
David Pommerenke, Missouri University of Science and Technology
Jian Min Zhang
Ramachandran Chundru

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The use of high-speed logic makes modern electronic systems highly susceptible to electrostatic discharge (ESD). Because of their wider bandwidth, faster digital devices are more susceptible to high frequency ESD transient fields. In the analysis of ESD problems, an exact knowledge of the affected PINs and nets is essential for an optimal solution. A three dimensional ESD scanning system, which has been developed to record the ESD susceptibility map for a printed circuit board, is presented, and the mechanisms that the ESD event couples into the digital devices is studied.