An Experimental Investigation of 4-Layer Printed Circuit Board Decoupling

Todd H. Hubing, Missouri University of Science and Technology
James L. Drewniak, Missouri University of Science and Technology
Michael J. Wilhelm
Thomas Van Doren, Missouri University of Science and Technology
Fei Sha

This document has been relocated to

There were 13 downloads as of 28 Jun 2016.


This paper examines the measured power bus impedance of fully populated 4-layer printed circuit boards with internal power and ground planes. Three boards provided by two leading computer companies were evaluated. Each of the state-of-the-art high-speed boards used in this study employed surface-mount decoupling capacitors to reduce noise on the power bus. The boards were measured with and without some or all of their decoupling capacitance. The effectiveness of the decoupling capacitors as a function of location and frequency and the relationship between board impedance and power bus noise was explored. The behavior of 4-layer boards is shown to be quite different than that of boards without planes or boards with closely spaced planes.