Swarm Intelligence for Digital Circuits Implementation on Field Programmable Gate Arrays Platforms

Ganesh K. Venayagamoorthy, Missouri University of Science and Technology
Venu Gopal Gudise

This document has been relocated to http://scholarsmine.mst.edu/ele_comeng_facwork/1898

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Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize the FPGA's resources is an efficient placement and routing mechanism. This paper presents an optimization technique based on swarm intelligence for FPGA placement and routing. Mentor graphics technology mapping netlist file is used to generate initial FPGA placements and routings which are then optimized by particle swarm optimization (PSO). Results for the implementation of a binary coded decimal bidirectional counter and an arithmetic logic unit on a Xilinx FPGA show that PSO is a potential technique for solving the placement and routing problem.