A Circuit Model for ESD Performance Analysis of Printed Circuit Boards

Byong-Su Seol
Jong-Sung Lee
Jae-Deok Lim
Hyungseok Lee
HarkByeong Park
Argha Nandy
David Pommerenke, Missouri University of Science and Technology

This document has been relocated to http://scholarsmine.mst.edu/ele_comeng_facwork/695

There were 71 downloads as of 22 Jun 2016.


This paper provides a SPICE-compatible circuit model for characterizing electrostatic discharge (ESD) clamping performance of protection devices mounted on printed circuit boards (PCBs). An equivalent circuit model for a commercial ESD generator is introduced and a simulation methodology of an ESD protection device with non-linear resistance characteristic using voltage controlled current source is described. These models combined to create a full circuit model with a PCB model in a SPICE-like circuit simulator. Comparison results between the simulated and measured are presented to verify the accuracy of the proposed circuit model. A trade-off analysis between the ESD clamping performance and signal integrity with the ESD protection device in high-speed applications is also presented as a case study.