NCL Implementation of Dual-Rail 2S Complement 8Ã8 Booth2 Multiplier using Static and Semi-Static Primitives

Mandar V. Joshi
V. Jegadeesan
A. Basu
S. Jaiswal
Waleed K. Al-Assadi, Missouri University of Science and Technology
S. C. Smith
Sagar R. Gosavi

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In this work, we use static and semi-static versions of NULL Convention Logic (NCL) primitives (i.e., threshold gates) to implement a dual-rail 8times8 2s complement multiplier using the Modified Booth2 algorithm for partial product generation and a Wallace tree for partial product summation. We establish the multiplier's functionality utilizing VHDL-based simulations of the gate-level structural design. The design is then implemented at the transistor-level and layout-level using both static and semi-static threshold gates, for a 1.8V 0.18mum TSMC CMOS process; and these two implementations are compared in terms of area, power, and speed.