A Bipartite, Differential I DDQ Testable Static RAM Design

Waleed K. Al-Assadi, Missouri University of Science and Technology
A. P. Jayasumana
Y. K. Malaiya

This document has been relocated to http://scholarsmine.mst.edu/ele_comeng_facwork/1335

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I DDQ (Defect Detection by Quiescent power supply current measurement), or current testing, has emerged in the last few years as an effective technique for detecting certain classes of faults in high-density ICs. In this paper, a testable design that enhances the I DDQ testability of static random access memories (SRAMs) for off-line testing as proposed. To achieve high accuracy and a test speed approaching the system operational speed, the memory is partitioned for comparison of I DDQ values. Parallel write/read operations are used to activate possible faults, while quiescent power supply currents from two blocks are compared