Recently, we proposed a new clock-free nanowire crossbar architecture based on a delayinsensitive paradigm called Null Convention Logic (NCL). The proposed architecture has simple periodic structure that is suitable for non-deterministic nanoscale assembly and does not require a clock distribution network - so it is intrinsically free from timing-related failure modes. Even though the proposed architecture offers improved manufacturability, it is still not free from defects. This paper elaborates on the different programming techniques to map a given threshold gate macro on a random PGMB (Programmable Gate Macro Block) with predefined dimension. Defect-Aware and Defect Unaware approaches have been considered to map a given threshold gate onto a PGMB without affecting its functionality. Defect aware approach uses a defect map, gate table which help in efficient programming and also conservative use of resources. Defect unaware approach on the other hand is faster than defect aware approach, does not use defect maps and is not as efficient as defect aware approach. Parametric simulation results using MATLAB are used to show the programmability of these approaches under various circumstances.

Meeting Name

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (2007: Sep. 26-28, Rome, Italy)


Electrical and Computer Engineering

Keywords and Phrases

Circuit Layout; Fault Tolerance; Logic Circuits; Nanowires; Manufacturability; Nanoscale Assemblies; Nanowire Crossbars; Null Convention Logic; Parametric Simulations; Programmable Gate; Programming Technique; Proposed Architectures; Architecture; Clock Distribution Networks; Clocks; MATLAB; Threshold Logic; Defects

International Standard Book Number (ISBN)


International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2007 IEEE Computer Society, All rights reserved.

Publication Date

01 Sep 2007