Abstract
This article investigated the effects of local solder-mask and overlay structure changes on crosstalk. This structure is based on a four-layer high-speed PCB on a computer DDR5 board. Our goal is to use the obtained simulation results to locate the optimal response that not only meets the performance requirements but is also robust to geometric changes caused by manufacturing tolerances. These two methods have a good correlation with the simulation results and show strong capabilities in the practical applications.
Recommended Citation
Z. Lin et al., "Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT," 2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020, pp. 586 - 590, article no. 9191478, Institute of Electrical and Electronics Engineers, Jul 2020.
The definitive version is available at https://doi.org/10.1109/EMCSI38923.2020.9191478
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Coverlay; DDR5; Far-end crosstalk (FEXT); microstrip line; printed circuit board (PCB); soldermask
International Standard Book Number (ISBN)
978-172817430-3
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Jul 2020
Comments
Intel Corporation, Grant 20YYJC2759