Abstract
Modeling ESD protection using the System Efficient ESD Design (SEED) methodology enables optimal protection of an IO using TVS and external components. The success of modeling depends on the accuracy of the models. This work shows improvements to SPICE models used to characterize TVS diodes and IC I/O. The improvement is twofold. The transition phases between snapback and main current flow have been adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve are included. The model is capable of operating in generic SPICE and being tested in ADS and LT-SPICE. The paper explains this in detail to enable the reader to apply this modeling principle.
Recommended Citation
A. Pak et al., "Improvement of SPICE based ESD Protection Models for I/O Protection Modeling," 2021 Joint IEEE International Symposium on Electromagnetic Compatibility Signal and Power Integrity, and EMC Europe, EMC/SI/PI/EMC Europe 2021, pp. 1006 - 1011, Institute of Electrical and Electronics Engineers, Jul 2021.
The definitive version is available at https://doi.org/10.1109/EMC/SI/PI/EMCEurope52599.2021.9559224
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Electrostatic discharge; ESD protection; SEED; SPICE; TVS
International Standard Book Number (ISBN)
978-166544888-8
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
26 Jul 2021
