Decoupling Capacitor Optimization to Achieve Target Impedance in PCB PDN Design


With increasingly stringent requirements for lower voltage supply, and higher density in PCB (Printed Circuit) PDN (Power Distribution Network) design, power integrity has an increasingly important role in PCB design. The PI performance of the PCB design must meet requirements, or modification and trial-and-error are necessary to ensure the target impedance is satisfied. Lots of design practices and commercial tools are utilized to aid PI designers, e.g., developing a suitable stack-up, saving cost while placing enough decoupling capacitors, best layout for IC pins and so on. It is essential in the PCB PDN design to place as fewer decoupling capacitors as possible to achieve target impedance and voltage ripple goals while saving cost. In this paper, the influence from the types of decoupling capacitor and stack-up is considered. The variety of decoupling capacitors contributes to the objective of reaching the target with minimum number of decoupling capacitors.

Meeting Name

2021 IEEE International Joint Electromagnetic Compatibility Signal and Power Integrity and EMC Europe Symposium, EMC/SI/PI/EMC Europe 2021 (2021: Jul. 26-Aug. 13, Raleigh, NC)


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory


National Science Foundation, Grant IIP-1916535

Keywords and Phrases

Cavity Model; Decoupling Capacitor; Design Considerations; PDN Impedance; Power Distribution Network (PDN); Stack-Up

International Standard Book Number (ISBN)


Document Type

Article - Conference proceedings

Document Version


File Type





© 2021 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

13 Aug 2021