Resistance Modeling for Striplines with Different Surface Roughness on the Planes


To model additional conductor loss due to foil surface roughness various empirical or physical models have been brought up to provide surface roughness correction factors for the per-unit-length (PUL) resistance assuming certain roughness of foil conductors. However for striplines on typical printed circuit board, different sides of the traces and references planes may have different surface roughness levels due to the fabrication process. Traditionally engineers may calculate surface roughness correction factors using averaged roughness level of the upper and lower sides of the trace. However this empirical estimation may lead to inaccurate modeling results especially when the stripline is not vertically symmetrical or the differences among the roughness levels of planes are significant. In this project, a methodology is presented to calculate the resistance of a stripline with different surface roughness levels on upper and lower sides of the trace and reference planes. After separating the resistances contributed by different smooth planes, each plane's resistance is corrected independently using corresponding surface roughness correction factor. The stripline's resistance is obtained by combining the corrected resistances of different planes.

Meeting Name

2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity, EMCSI 2020 (2020: Jul. 27-31, Virtual)


Electrical and Computer Engineering


National Science Foundation, Grant IIP-1916535

Keywords and Phrases

Printed Circuit Boards; Signal Integrity; Skin Effect; Striplines; Surface Roughness

International Standard Book Number (ISBN)


Document Type

Article - Conference proceedings

Document Version


File Type





© 2020 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

10 Sep 2020