Fault Isolation of Short Defect in Through Silicon Via (TSV) based 3D-IC
Development of through silicon via (TSV) based 3 dimensional integrated circuit (3D-IC) has allowed reduction of form factor and power consumption with higher data transmission speed. Despite the great advantages, various types of defects cannot be avoided in continuously reducing scale of the components. The performance degradation caused by defects has to be analyzed to increase the yield of the products. In this paper, the effect of short defect in TSV channel is analyzed in frequency- and time-domain. A GSG-type daisy-chain structure with eight TSVs per channel is designed for 3D EM simulation and the results are obtained in S-parameter curves and TDR waveforms. Using 2-port analysis, the results from two ends of the channel are compared. The location of short defect is varied for case analysis. Under the assumption that the defect is located closer to one port than the other, the asymmetric structure results in distinguishable S11 and S22. Similarly, TDR waveforms from port 1 and port 2 are compared for fault isolation. By taking the difference between the results from port 1 and port 2, the short defect in TSV channel can be accurately detected and isolated.
D. H. Jung et al., "Fault Isolation of Short Defect in Through Silicon Via (TSV) based 3D-IC," Proceedings of the 2013 IEEE International 3D Systems Integration Conference (2013, San Francisco, CA), Institute of Electrical and Electronics Engineers (IEEE), Oct 2013.
The definitive version is available at https://doi.org/10.1109/3DIC.2013.6702376
2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 (2013: Oct. 2-4, San Francisco, CA)
Electrical and Computer Engineering
Keywords and Phrases
3D-IC; Fault Isolation; Short Defect; TSV
International Standard Book Number (ISBN)
Article - Conference proceedings
© 2013 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
04 Oct 2013