Title

Area Efficient Multi-Threshold Null Convenction Logic

Abstract

Multi-Threshold null convention logic (MTNCL) is a commonly used asynchronous paradigm for designing low power NCL circuits. Traditionally, MTNCL circuits implemented using complementary metal oxide semiconductor (CMOS) technique that tends to occupy a large area. To address this limitation, a gate diffusion input (GDI) methodology is introduced for implementing MTNCL circuits. This GDI technique enables complex logic to be implemented using only two transistors that helps to reduce area utilization. In this paper, a novel approach to implement MTNCL designs based GDI methodology is proposed. The proposed approach has been verified by implementing TH23 MTNCL gate. Comparing to the conventional CMOS implementation, the proposed approach shows a 45% reduction in the area overhead.

Meeting Name

16th International System-on-Chip Design Conference, ISOCC 2019 (2019: Oct. 6-9, Jeju, South Korea)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Cadence; CMOS; Gate Diffusion Input; Multi-Threshold NULL Convention Logic

International Standard Book Number (ISBN)

978-172812478-0

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2019 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Oct 2019

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