Jitter-Aware Target Impedance
A new concept of target impedance which directly correlates the I/O buffer output jitter with the power distribution network (PDN) design is proposed. Jitter-ware target impedance is derived from the time domain waveform of power voltage ripple and the maximum allowable jitter assuming the single stage buffer as a RC network, which is then applied to the PDN design given a certain jitter specification. From HSPICE simulation of transient switching current, PDN impedance and power voltage ripple, it is shown that the proposed jitter-aware target impedance successfully correlates power supply induced jitter (PSIJ) and PDN impedance parameters with a simple analytical expression.
Y. Sun et al., "Jitter-Aware Target Impedance," Proceedings of the 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity (2019, New Orleans, LA), pp. 217-222, Institute of Electrical and Electronics Engineers (IEEE), Jul 2019.
The definitive version is available at https://doi.org/10.1109/ISEMC.2019.8825313
2019 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, EMC+SIPI 2019 (2019: Jul. 22-26, New Orleans, LA)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Power Distribution Network (PDN); Power Supply Induced Jitter; Switching Current; Target Impedance
International Standard Book Number (ISBN)
Article - Conference proceedings
© 2019 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Jul 2019