Far-End Crosstalk Mitigation in DDR5 using Graphene-Paraffin Material Coated Signal Lines with Tabs


With improvement in high-density and high-speed printed circuit boards (PCBs), far-end crosstalk (FEXT) problem is one of most critical factors affecting signal quality. This is main because the spacing between adjacent signal lines becomes very small, such as the PCB routes in the fifth generation double data rate technology (DDR5). In this paper, a new method is developed for the mitigation of FEXT in DDR5. First, we investigate two cases, i.e., tabs added on the signal lines and graphene-paraffin materials coated signal lines with tabs. From the simulated S-parameters, the associated FEXT can be suppressed in a very wide frequency range (0∼16GHz). Then, graphene-paraffin material is added on signal lines with tabs to further improve the performance. The FEXT can be decreased more than 12dB around 3.2GHz, compared with the traditional signal routing. It has been demonstrated by the final results in both frequency and time domains that, our structure has succeeded in mitigating FEXT in DDR5, in comparison with previous techniques. Thus, this method has a great potential in FEXT mitigation in DDR5.

Meeting Name

2019 Cross Strait Quad-Regional Radio Science and Wireless Technology Conference, CSQRWC 2019 (2019: Jul. 18-19, Taiyuan, China)


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory


This work is supported by Intel Corporation.

Keywords and Phrases

DDR5; Far-End Crosstalk (FEXT); Graphene-Paraffin Material; High-Density PCBs; Mitigation; Tabs

International Standard Book Number (ISBN)


Document Type

Article - Conference proceedings

Document Version


File Type





© 2019 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jul 2019