Systematic Analysis of ESD-Induced Soft-Failures as a Function of Operating Conditions


Electrostatic discharges (ESD) to parts of a system can lead to system-level soft-failures. These failures can depend on the activity of the system at the moment of discharge. This paper investigates ESD susceptibility as a function of different operating conditions such as software loading, clock frequency, and VDD voltage. Due to the large number of possible conditions, a commercial automated ESD scanner is modified and used to obtain ESD susceptibility maps for each operating condition. The core processor of a single-board computer is selected as the device under test. It is observed that the processor becomes more sensitive to ESD events as its software loading increases. The effect of VDD voltage and clock frequency on the sensitivity of the processor is also discussed. Moreover, the effect of increasing the power distribution network impedance and noise is investigated, partially leading to counterintuitive results.

Meeting Name

2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility, EMC/APEMC 2018 (2018: May 14-18, Singapore, Singapore)


Electrical and Computer Engineering


This material is based upon work supported by the National Science Foundation (NSF) under Grants IIP-1440110.

Keywords and Phrases

Clocks; Electric discharges; Electromagnetic compatibility; Electrostatic discharge; Laser optics; Different operating conditions; Electro-Static Discharge (ESD); Operating condition; Power distribution network impedance; Single board computers; Soft failure; Susceptibility maps; Transmission line pulse; Electrostatic devices; Soft-failure; Transmission line pulse generator

International Standard Book Number (ISBN)


Document Type

Article - Conference proceedings

Document Version


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© 2018 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 May 2018