An Application of System Level Efficient ESD Design for High- Speed USB3.x Interface
A high-speed USB3.x IO is analyzed using the System level efficient ESD design methodology  using on-board current and voltage measurements for the TX and RX pins. The interactions between external ESD protection device and the on-chip ESD protection circuit is investigated in measurement and simulation.
P. Wei et al., "An Application of System Level Efficient ESD Design for High- Speed USB3.x Interface," Proceedings of the 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (2018, Reno, NV), ESD Association, Sep 2018.
The definitive version is available at https://doi.org/10.23919/EOS/ESD.2018.8509765
2018 40th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018 (2018: Sep. 23-28, Reno, NV)
Electrical and Computer Engineering
Keywords and Phrases
Design; Design Methodology; ESD protection devices; High Speed; Measurement and simulation; On-chip ESD protection; System levels; Electrostatic devices
International Standard Book Number (ISBN)
International Standard Serial Number (ISSN)
Article - Conference proceedings
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01 Sep 2018