Through-Silicon Via Capacitance-Voltage Hysteresis Modeling for 2.5-D and 3-D IC
We propose, for the first time, an explicit semiconductor physics-based through-silicon via (TSV) capacitance-voltage (CV) model. The effect of TSV CV hysteresis is demonstrated in the model, and the TSV capacitance is modeled with respect to dc bias voltage and the dimension of the TSV. The proposed model is verified by comparison to the measurement results. The effect of hysteresis in the model correlates well with the measurement results. This model can be utilized in a circuit level simulation to expand the possible application of the model to, but not limited to, hierarchical power distribution network impedance analysis, RC delay analysis, input-output power consumption analysis, and crosstalk and eye diagram simulation in any 3-D-IC systems using TSVs.
D. Kim et al., "Through-Silicon Via Capacitance-Voltage Hysteresis Modeling for 2.5-D and 3-D IC," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 6, pp. 925-935, Institute of Electrical and Electronics Engineers (IEEE), Jun 2017.
The definitive version is available at https://doi.org/10.1109/TCPMT.2017.2670063
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Through-silicon via (TSV) technology; TSV capacitance-voltage (CV) hysteresis; TSV CV model
International Standard Serial Number (ISSN)
Article - Journal
© 2017 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Jun 2017