Modeling of through-Silicon Via (TSV) with an Embedded High-Density Metal-Insulator-Metal (MIM) Capacitor


In this paper, we, for the first time, modeled and analyzed through-silicon via (TSV) with an embedded high-density metal-insulator-metal (MIM) capacitor. For 2.5-D/3-D ICs, this technology could be a potential solution to improve electrical performance. We conduct the modeling and the proposed model were compared with an electromagnetic (EM) solver, to evaluate signal and power integrity (SI/PI). The analysis was performed based on the insertion loss and impedance in the frequency range from 0.01 GHz to 20 GHz. The dominant factors to determine the electrical characteristic were analyzed depending on the frequency range. In order to model the TSVs, the concept of loop inductance was applied. Then, the capacitance and conductance between the TSVs were calculated respectively including the MIM capacitance. From the results of modeling and EM simulations, it is predicted that the TSVs are beneficial to improve SI not PI. Because the equivalent capacitance is decreased in the low frequency range under 200 MHz and the equivalent conductance is increased in the high frequency range above 200 MHz.

Meeting Name

2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2018 (2018: Dec. 16-18, Chandigarh India)


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Impedance; Insertion loss; Metal-insulator-metal (MIM) capacitor; Silicon interposer; Through-silicon via (TSV)

International Standard Book Number (ISBN)


Document Type

Article - Conference proceedings

Document Version


File Type





© 2018 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Dec 2018