A SiGe-channel junctionless-accumulation-mode (JAM) PMOS bulk FinFETs were successfully demonstrated on Si substrate with PN junction-isolation scheme for the first time. The JAM bulk FinFETs with fin width of 18 nm exhibits excellent subthreshold characteristics such as subthreshold swing of 64 mV/decade, drain-induced barrier lowering (DIBL) of 40 mV/V and high Ion/Ioff current ratio ( > 1 x 105). The change of substrate bias from 0 to 5 V leads to the threshold voltage shift of 53 mV by modulating the effective channel thickness. When compared to the Si-channel bulk FinFETs with fin width of 18 nm, Si and SiGe channel devices exhibits comparable subthreshold swing and DIBL. For devices with longer fin width, SiGe channel devices exhibits much lower DIBL, indicating superior top-gate controllability and robustness to substrate bias compared to the Si channel devices. A zero temperature coefficient point was observed in the transfer curves as temperature increases from -120 to 120°C, confirming that mobility degradation is dominantly affected by phonon scattering mechanism.
D. Kim et al., "First Demonstration of Ultra-Thin SiGe-Channel Junctionless Accumulation-Mode (JAM) Bulk FinFETs on Si Substrate with PN Junction-Isolation Scheme," Journal of the Electron Devices Society, vol. 2, no. 5, pp. 123-127, Institute of Electrical and Electronics Engineers (IEEE), Sep 2014.
The definitive version is available at https://doi.org/10.1109/JEDS.2014.2326560
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
junction-isolation; Junctionless (JL) field-effect transistor (FET); junctionless-accumulation-mode (JAM) FET; SiGe bulk FinFET
International Standard Serial Number (ISSN)
Article - Journal
© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Sep 2014