Algorithm for Extracting Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling and Robustness Analysis


This paper explains the extraction from the measurement of the parameters necessary in time domain to identify the hysteretic behavior of the coupling capacitance of through silicon vias (TSVs). The algorithm was developed in such a way that the equivalent capacitance model can be implemented into standard circuit simulators. A comparison with a known procedure based on the genetic algorithm approach is offered as validation. Results showing the robustness of the algorithm and the effects of the hysteresis on the crosstalk among TSV and integrated circuit active devices are reported and discussed.


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Capacitance; Circuit simulation; Electronics packaging; Genetic algorithms (GA); Hysteresis; Parameter estimation; Reconfigurable hardware; Circuit simulators; Coupling capacitance; Equivalent capacitance; Extracting parameter; Genetic algorithm approach; Hysteretic behavior; Robustness analysis; Through silicon vias (TSVs); Three dimensional integrated circuits; Active devices; Dielectric hysteresis; Equivalent circuit modeling; Nonlinear effects; Signal integrity; Time domain

International Standard Serial Number (ISSN)

0018-9375; 1558-187X

Document Type

Article - Journal

Document Version


File Type





© 2017 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Nov 2017