CMOS IC Topology Design Verification by Heuristic Dynamic Programming (HDP)
The applications of non-standard logic device are increasing fast in the industry. Many of these applications require high speed, low power, functionality and flexibility, which cannot be obtained by standard logic device. These special logic cells can be constructed by the topology design strategy automatically or manually. However, the need arises for the topology design verification. The layout versus schematic (LVS) analysis is an essential part of topology design verification, and subcircuit extraction is one of the operations in the LVS testing. In this paper, a novel neural network based heuristic dynamic programming algorithm (SubHDP) on subsircuit extraction problem is proposed. To evaluate its performance, we compare the SubHDP with a non-neural approach. The run time of SubHDP algorithm is faster than the non-neural algorithm when the main circuit has no more than 20,000 transistors, however, when the main circuit has more than 20,000 transistors, the non-neural algorithm becomes faster.
N. Zhang et al., "CMOS IC Topology Design Verification by Heuristic Dynamic Programming (HDP)," Intelligent Engineering Systems Through Artificial Neural Networks, American Society of Mechanical Engineers (ASME), Nov 2002.
Artificial Neural Networks in Engineering Conference, ANNIE 2002 (2002: Nov. 10-13, St. Louis, MO)
Electrical and Computer Engineering
Keywords and Phrases
Non-Standard Logic Device; Special Logic Cells; Topology Design Verification
Article - Conference proceedings
© 2002 American Society of Mechanical Engineers (ASME), All rights reserved.
13 Nov 2002