Performance Evaluation of CNFET-Based Logic Gates
As the physical gate length of current devices is reduced to below 65 nm, effects (such as large parametric variations and increase in leakage current) have caused the I-V characteristics to be substantially depart from those commonly associated with traditional MOSFETs, thus impeding the efficient development and manufacturing of devices at deep submicro/nano scales. Carbon Nanotube Field Effect Transistors (CNFETs) have received widespread attention, as one of the promising technologies for replacing MOSFETs at the end of the Technology Roadmap. This paper presents a detailed simulationbased assessment of circuit performance of this technology and compares it to conventional MOSFETs; the designs of different logic gates and the full adder circuit are simulated under the same minimum gate length and different operational conditions. It is shown that the power-delay product (PDP) and the leakage power for the CNFET based gates are lower than the MOSFET based logic gates by 100 to 150 times, respectively. The CNFET based logic gates demonstrate good functionality even at a 0.3V power supply (while MOSFET based gates fail at 0.5V).
G. Cho et al., "Performance Evaluation of CNFET-Based Logic Gates," Proceedings of the IEEE International Instrumentation and Measurement Technology Conference (2009, Singapore), pp. 913-917, Institute of Electrical and Electronics Engineers (IEEE), May 2009.
The definitive version is available at https://doi.org/10.1109/IMTC.2009.5168580
IEEE International Instrumentation and Measurement Technology Conference: I2MTC (2009: May 5-7, Singapore)
Electrical and Computer Engineering
Keywords and Phrases
Carbon Nanotube Field-Effect Transistors (CNFETs); Circuit Performance; Fan-Out; Full Adders; Gate Length; IV Characteristics; Leakage Power; MOS-FET; MOSFETs; Operational Conditions; Parametric Variation; Performance Evaluation; Power Delay Product (PDP); Power Supply; Simulation-Based; Technology Roadmaps; Adders; Carbon Nanotubes; Leakage Currents; Logic Circuits; Logic Gates; Measurement Theory; MOSFET Devices; Nanosensors; Parametric Devices; Technological Forecasting; Technology; Field Effect Transistors; Delay; Fanout; Power; Temperature
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Article - Conference proceedings
© 2009 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 May 2009