Parallel Decoding for Multi-Stage BCH Decoder


3D heterogeneous processor (commonly termed as 3DHP) integrating multiple processor (such as CPU/GPU) and DRAM dies vertically interconnected by a massive number of Through-Silicon Vias (TSVs) is expected to address the limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability due to hotspots in on-chip thermal gradient may result in wide bit error rate variation in DRAM dies. A multi-path BCH decoder has been recently proposed to efficiently address this issue. In this paper, a novel parallel decoding approach for the Multi-Stage BCH decoder is proposed and validated. The proposed approach efficiently leverages the multiple decoding paths to decode multiple words and minimizes the overall decoding latency.

Meeting Name

International SoC Design Conference: ISOCC (2016: Oct. 23-26, Jeju, South Korea)


Electrical and Computer Engineering


National Science Foundation (U.S.)


This material is based upon work supported by the National Science Foundation under Grant No. CCF-1337167 and CCF-1539840, in part.

Keywords and Phrases

Bit Error Rate; Electronics Packaging; Energy Utilization; Image Coding; Parallel Processing Systems; Programmable Logic Controllers; Three Dimensional Integrated Circuits; BCH Decoders; Heterogeneous Processors; Limited Bandwidth; Multiple Decoding Paths; Multiple Processors; Parallel Decoding; Spatial and Temporal Variability; Through Silicon Vias; Decoding

International Standard Book Number (ISBN)

978-1509032198; 978-1509032204

Document Type

Article - Conference proceedings

Document Version


File Type





© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Oct 2016