Optimal Spare Utilization in Repairable and Reliable Memory Cores


Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies the largest portion of the SoC area; this trend much likely will continue in the future as it is widely anticipated that it will approach the 94% level by the year 2014. As memory cells are more prone to defects and faults than logic cells, redundancy has been extensively used for enhancing defect and fault tolerance through repair by spare (row and column) replacement. Unlike legacy PCB (printed circuit board) or MCM (multichip module) based systems, embedded cores cannot be physically replaced once they are fabricated onto a SoC. To realize both enhanced manufacturing yield and field reliability, ATE (automated test equipment) and BISR (built-in-self-repair) are utilized to allocate redundancy for the embedded memory cores. As ATEs (for the repair of manufacturing defects) and BISR (for repairing field faults) rely on the provided redundancy (rows and columns), spare partition and utilization techniques are proposed in this paper to achieve an optimal combination of yield and reliability for embedded memory cores. Parametric simulation results for the single dimensional (i.e., spare columns) and two-dimensional (i.e., both spare columns and rows) cases are provided.

Meeting Name

International Workshop on Memory Technology, Design and Testing (2003: Jul. 28-29, San Jose, CA)


Electrical and Computer Engineering

Keywords and Phrases

Application Specific Integrated Circuits; Built-In Self Test; Defects; Embedded Systems; Equipment Testing; Fault Tolerance; Legacy Systems; Logic Devices; Manufacture; Memory Architecture; Microprocessor Chips; Multichip Modules; Printed Circuit Boards; Printed Circuits; Programmable Logic Controllers; Redundancy; Reliability; Repair; Automated Test Equipment; Built-In-Self-Repair; Defect and Fault Tolerances; Embedded Memory; High Performance Systems; Memory Core; System-on-Chip Technology; Yield; System-on-Chip; Embedded Memory Repair and Reliability; Fault-Tolerant Memory Core

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International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version


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© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jul 2003