On-Chip Aging Prediction Circuit in Nanometer Digital Circuits
In nanometer technology, accurate circuit aging prediction of MOSFET digital circuits caused by aging phenominon is one of the most critical issues for more reliable adaptive tuning system design. This paper proposes a new on-chip aging sensor circuit to predit and detect a circuit failure caused by BTI and HCI aging effects on digital circuits. The proposed circuit is based on timing warning windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur.
B. Jang et al., "On-Chip Aging Prediction Circuit in Nanometer Digital Circuits," Proceedings of the International SoC Design Conference (2014, Jeju, South Korea), pp. 68-69, Institute of Electrical and Electronics Engineers (IEEE), Nov 2014.
The definitive version is available at https://doi.org/10.1109/ISOCC.2014.7087599
International SoC Design Conference: ISOCC (2014: Nov. 3-6, Jeju, South Korea)
Electrical and Computer Engineering
IC Design Education Center (IDEC)
Keywords and Phrases
Digital Circuits; Integrated Circuits; MOSFET Devices; Programmable Logic Controllers; Adaptive Tuning; Aging Effects; Circuit Aging; Circuit Failures; Critical Issues; Guard-Band; Nanometer Technology; Sensor Circuit; Timing Circuits; Aging Effect; Aging Sensor; Guardband Violation
International Standard Book Number (ISBN)
Article - Conference proceedings
© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Nov 2014