Novel Functional Testing Technique for Asynchronous Nanowire Crossbar System


The recently proposed asynchronous nanowire clock-free crossbar architecture is envisioned to enhance the manufacturability and to improve the robustness of digital circuits by removing various timing-related failure modes. Even though the proposed clock-free architecture has numerous merits over its clocked counterpart, it is still not free from high defect rates inherently induced by nondeterministic nanoscale assembly. In order to address this issue, a novel functional test scheme for validating threshold gates on Programmable Gate Macro Blocks (PGMB) has been proposed. The main aim of this paper is to present a test algorithm that can be used to identify manufacturing defects at programmable locations on a PGMB. In addition, this paper also presents several replacement and re-arrangement schemes to enable true realization of threshold gates. Specific figures of merits have also been coined to quantify the performance of the algorithm. This is a very significant step towards efficient defect testing since the earlier existing test scheme failed to provide any significant breakthrough as far as testing mechanisms were concerned. The proposed approach tests only the crosspoints programmed as ON state using input patterns unique to the given threshold gate macro. The proposed scheme helps achieve correct programmability with minimal test overhead. This test scheme can be used to assure the true functionality of any threshold gate on a given PGMB. The proposed scheme is anticipated to provide high fault coverage and excellent fault tolerance. These findings have been backed by parametric simulation results using MATLAB.

Meeting Name

IEEE International Instrumentation and Measurement Technology Conference: I2MTC (2009: May 5-7, Singapore)


Electrical and Computer Engineering

Keywords and Phrases

Asynchronous Nanowire Crossbar System; Crossbar Architecture; Defect Rate; Fault Coverages; Figures of Merits; Functional Test; Functional Testing; Input Patterns; Macro Block; Manufacturability; Manufacturing Defects; Nanoscale Assemblies; Parametric Simulation; Programmability; Programmable Gate; Re-Arrangement; Test Algorithms; Test Scheme; Testing Mechanism; Threshold Gates; Crossbar Equipment; Defects; Digital Integrated Circuits; Failure Analysis; Fault Tolerant Computer Systems; MATLAB; Measurement Theory; Nanowires; Quality Assurance; Resonant Tunneling; Testing; Threshold Logic; Timing Circuits; Fault Tolerance; Defect and Fault-Tolerance; Parametric Simulation

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International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version


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© 2009 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 May 2009