Latency/Area Analysis and Optimization of Asynchronous Nanowire Reconfigurable Crossbar System
With continued scaling of complementary metal-oxide-silicon (CMOS) technology, numerous challenges have arisen making it difficult to progress with. These challenges include the increase of integrated circuit complexity, non-recoverable expenses, frequency and power density. Nanotechnologies are expected to take the forefront of continuing the technological revolution. In this work, a novel model-based latency/area analysis and optimization method for the newly proposed Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) is presented and validated. ANRCA is based on a self-timed logic referred to as the Null Convention Logic (NCL). There is no global clocking and clock distribution network, all failure modes related to timing will be either eliminated or relaxed. The proposed architecture is anticipated to have higher manufacturability and robustness that are critical factors in nanoscale systems due to the nondeterministic nature of nanoassemblies and also suitable computing frameworks for asynchronous nanoscale communication networks. In order to facilitate efficient programming and flexible reconfiguration, a new hierarchical reconfigurable architecture for ANRCA is also proposed. Various configurable logic block structures have been considered and also their programming and reconfiguration issues are discussed. The proposed measurement and optimization method can be used to estimate area and latency measurements for different configurable logic blocks and also applied to find the optimal structure for the given arbitrary logic to map.
J. Wu and M. Choi, "Latency/Area Analysis and Optimization of Asynchronous Nanowire Reconfigurable Crossbar System," Nano Communication Networks, vol. 1, no. 4, pp. 301 - 309, Elsevier, Dec 2010.
The definitive version is available at https://doi.org/10.1016/j.nancom.2011.01.003
Electrical and Computer Engineering
National Science Foundation (U.S.)
Keywords and Phrases
Area/Latency Measurement; Asynchronous Computing; Communication Networks; Computing Frameworks; Configurable Logic Blocks; Critical Factors; Crossbar Architecture; Flexible Reconfiguration; Manufacturability; Metal-Oxide; Model-Based; Nano Scale; Nano-Assemblies; Nano-Scale System; Null Convention Logic (NCL); Optimal Structures; Optimization Method; Power Densities; Proposed Architectures; Re-Configurable; Reconfigurable Architecture; Reconfigurable Logic; Self-Timed; Technological Revolution; Clock Distribution Networks; Differentiating Circuits; Failure Analysis; Fault Tolerance; Nanostructured Materials; Nanowires; Network Architecture; Quality Assurance; Structural Optimization; Nanowire Crossbar; Optimization
International Standard Serial Number (ISSN)
Article - Journal
© 2010 Elsevier, All rights reserved.
01 Dec 2010