Latency & Area Measurement and Optimization of Asynchronous Nanowire Crossbar System
In this work, a novel model-based latency/area measurement and optimization method for the newly proposed Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) is presented and validated. ANRCA is based on a self-timed logic referred to as the Null Convention Logic (NCL). Since there is no global clocking and clock distribution network, all failure modes related to timing will be either eliminated or relaxed. The proposed architecture is anticipated to have higher manufacturability and robustness that are critical factors in nanoscale systems due to nondeterministic nature of nanoassembly. In order to facilitate efficient programming and flexible reconfiguration, a new hierarchical reconfigurable architecture for ANRCA is also proposed. Various configurable logic block structures have been considered and also their programming and reconfiguration issues are discussed. The proposed measurement and optimization method can be used to estimate area and latency measurements for different configurable logic blocks and also applied to find the optimal structure for the given arbitrary logic to map. As a case study, a full adder (i.e., combinational logic block) with input and output registrations (i.e., sequential elements) has been implemented on the proposed configurable logic block structures to validate the proposed measurement and optimization method.
J. Wu and M. Choi, "Latency & Area Measurement and Optimization of Asynchronous Nanowire Crossbar System," Proceedings of the IEEE International Instrumentation and Measurement Technology Conference (2010, Austin, TX), pp. 1596 - 1601, Institute of Electrical and Electronics Engineers (IEEE), May 2010.
The definitive version is available at https://doi.org/10.1109/IMTC.2010.5488108
IEEE International Instrumentation and Measurement Technology Conference: I2MTC (2010: May 3-6, Austin, TX)
Electrical and Computer Engineering
National Science Foundation (U.S.)
Keywords and Phrases
Area Measurement; Area/Latency Measurement; Asynchronous Computing; Clock Distribution Network; Combinational Logic Blocks; Configurable Logic Blocks; Critical Factors; Crossbar Architecture; Flexible Reconfiguration; Full Adders; Input and Outputs; Manufacturability; Model-Based; Nano-Assemblies; Nano-Scale System; Null Convention Logic (NCL); Optimal Structures; Optimization Method; Proposed Architectures; Re-Configurable; Reconfigurable Architecture; Reconfigurable Logic; Self-Timed; Sequential Elements; Adders; Differentiating Circuits; Distributed Parameter Networks; Failure Analysis; Instruments; Measurement Theory; Nanowires; Network Architecture; Structural Optimization; Nanowire Crossbar; Optimization
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International Standard Serial Number (ISSN)
Article - Conference proceedings
© 2010 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 May 2010