Cost-Driven Optimization of Coverage of Combined Built-In Self-Test/Automated Test Equipment Testing


As the complexity of design and fabrication for instrumentation-on-silicon systems increases, the optimization of a combined Built-In Self-Test (BIST) and Automated Test Equipment (ATE) process is desirable to meet the high fault coverage while preserving acceptable costs. For digital systems, the costs associated with a combined BIST/ATE testing process mainly consist of the following components: 1) the cost due to the BIST area overhead and 2) the cost due to the overall test time. In general, BIST is faster than ATE, but it can provide only a limited fault coverage; for attaining a higher fault coverage from BIST, additional area (at a corresponding higher cost) is required. However, a higher fault coverage can usually be achieved from ATE, but excessive use of ATE results in additional test time (as an increased cost). The fault coverage of BIST and ATE plays a significant role, because it can affect the area overhead in BIST and the test time in BIST/ATE. This paper proposes a novel numerical method to find the optimized fault coverage by BIST and ATE so that minimal cost can be achieved. The proposed method is then applied to two parallel combined BIST/ATE testing schemes to ensure its validity.


Electrical and Computer Engineering

Keywords and Phrases

Automatic Testing; Built-In Self Test (BIST); Design for Testability; Fabrication; Optimization; Silicon on Insulator Technology; Automated Test Equipment (ATE); Fault Coverage; Equipment Testing; Combined BIST/ATE; Yield

International Standard Serial Number (ISSN)

0018-9456; 1557-9662

Document Type

Article - Journal

Document Version


File Type





© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jun 2007