Power Integrity Concepts for High-Speed Design on Multi-Layer PCBs
This article consists of a collection of slides from the author's conference presentation. Some of the specific areas/topics discussed include: PI module; PDN problem; geometry and inductance decomposition; PCB PDN design; circuit model behavior; logic transitions; voltage switching-dynamic current draw distrubances; conduction current path; power plane and capacitor location matrix; power plane location in layer stack; capacitor location; SMT decoupling; SMT capacitors; PCB PDN circuit model; voltage ripple separation; and package design flow.
J. L. Drewniak, "Power Integrity Concepts for High-Speed Design on Multi-Layer PCBs," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity (2017, Washington, D.C.), Institute of Electrical and Electronics Engineers (IEEE), Aug 2017.
The definitive version is available at https://doi.org/10.1109/ISEMC.2017.8078091
IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity (2017: Aug. 7-11, Washington, DC)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Integrated Circuits; Capacitors; Physics; Pins; Jitter; Geometry; Electromagnetic Compatibility; High-Speed Integrated Circuits; Integrated Circuit Packaging; Printed Circuit Design; Surface Mount Technology; Multilayer PCB; Power Integrity; High-Speed Design; PI Module; PDN Problem; Geometry Decomposition; Inductance Decomposition; PCB PDN Design; Circuit Model Behavior; Logic Transitions; Voltage Switching-Dynamic Current Draw Disturbances; Conduction Current Path; Capacitor Location Matrix; Power Plane Location; Layer Stack; SMT Decoupling; SMT Capacitors; PCB PDN Circuit Model; Voltage Ripple Separation; Package Design Flow
International Standard Book Number (ISBN)
International Standard Serial Number (ISSN)
Article - Conference proceedings
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01 Aug 2017