Modeling and Design of Buried Capacitances for Power Distribution Networks on Multilayer Printed Circuit Board
The engineering of the power delivery network is becoming a fundamental issue in the design of high speed digital systems on printed circuit boards (PCB). In fact, providing the required noise free voltage level to the different integrated circuits (IC) on a PCB system allows achieving the correct functioning of the systems and the desired performance as well. Several decoupling strategies can be employed for this crucial design goal, i.e., local decoupling, global decoupling [1,2] and buried capacitances. Due to improvements in the manufactory processes and cost reduction, the employment of buried capacitance as a decoupling strategy is becoming a more viable solution, being a buried capacitance just a pair of solid planes separated by distances on the order of few mils or less, therefore the less complicated solution.
G. Selli et al., "Modeling and Design of Buried Capacitances for Power Distribution Networks on Multilayer Printed Circuit Board," Proceedings of DesignCon 2006 (2006, Santa Clara, CA), vol. 1, pp. 429-446, UBM Electronics, Feb 2006.
DesignCon 2006 (2006: Feb. 6-9, Santa Clara, CA)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Design Goal; High-Speed Digital Systems; Multilayer Printed Circuit Board; Power Delivery Network; Power Distribution Network; Viable Solutions; Voltage Levels; Capacitance; Design; Electric Power Transmission; Organic Pollutants; Polychlorinated Biphenyls; Printed Circuit Boards
International Standard Book Number (ISBN)
Article - Conference proceedings
© 2006 UBM Electronics, All rights reserved.
01 Feb 2006