Design and Modeling for Chip-to-Chip Communication at 20 Gbps


This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.

Meeting Name

IEEE International Symposium on Electromagnetic Compatibility (2010: Jul. 25-30, Fort Lauderdale, FL)


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Chip-to-Chip Communications; Design And Modeling; Design Rules; FR4 Substrates; High-Speed Channels; Low Loss; Micro-Probes; New Technologies; S-Parameters; Substrate Material; Time Domain; Design; Electromagnetic Compatibility; Electromagnetism; Electronic Equipment Manufacture; Printed Circuit Design; Scattering Parameters; Printed Circuit Boards

International Standard Book Number (ISBN)

978-1424463053; 978-1424463084

International Standard Serial Number (ISSN)

2158-1118; 2158-110X

Document Type

Article - Conference proceedings

Document Version


File Type





© 2010 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jul 2010