Design and Modeling for Chip-to-Chip Communication at 20 Gbps
This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.
J. Zhang et al., "Design and Modeling for Chip-to-Chip Communication at 20 Gbps," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2010, Fort Lauderdale, FL), pp. 467-472, Institute of Electrical and Electronics Engineers (IEEE), Jul 2010.
The definitive version is available at https://doi.org/10.1109/ISEMC.2010.5711320
IEEE International Symposium on Electromagnetic Compatibility (2010: Jul. 25-30, Fort Lauderdale, FL)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Chip-to-Chip Communications; Design And Modeling; Design Rules; FR4 Substrates; High-Speed Channels; Low Loss; Micro-Probes; New Technologies; S-Parameters; Substrate Material; Time Domain; Design; Electromagnetic Compatibility; Electromagnetism; Electronic Equipment Manufacture; Printed Circuit Design; Scattering Parameters; Printed Circuit Boards
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Article - Conference proceedings
© 2010 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Jul 2010