A Vectorless Approach for Predicting Switching Activity in a Digital Circuit

Abstract

Existing vectorless methods use a statistical approach to estimate the average number of switching events in a digital circuit. While these methods allow one to predict the average power consumption, a critical parameter for many digital designs, they cannot be used to predict the statistical variation in power consumed in each clock cycle, which is necessary to estimate the bounds on power supply noise. A vectorless method is proposed for estimating the variance in the number of switching events across a digital design. This result may be used to estimate variance in power supply noise. The approach was tested on a 5 x 5 adder array. The standard deviation in the total number of switching events can be found within 1% for this design. Including covariance among switching events at different gates was critical. When covariance was ignored, the standard deviation was underestimated by nearly 84%. The proposed approach allows rapid estimation of a reasonable worst case number of switching events that may occur in a single clock cycle.

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Clocks; Digital circuits; Forecasting; Integrated circuits; Reconfigurable hardware; Statistics; Digital designs; Power-supply noise; Rapid estimation; Single-clock-cycle; Standard deviation; Statistical approach; Statistical variations; Switching activities; Switching; FPGA; noise analysis; power modeling and estimation; statistical estimation

International Standard Serial Number (ISSN)

0018-9375

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jun 2016

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