System-Level Modeling for Transient Electrostatic Discharge Simulation
This paper introduces an improved electrostatic discharge (ESD) system-level transient simulation modeling method and discusses its validation using IEC 61000-4-2 ESD pulses on a real-world product. The system model is composed of high current and broadband (up to 3 GHz) models of R, L, C, ferrite beads, diodes, and integrated circuit IO pins. A complex return path model is the key to correctly model the system's response to the IEC excitation. The model includes energy-limited time-dependent IC damage models. A power-time integral method is introduced to accurately determine if a junction would experience thermal runaway under an arbitrary injection waveform. The proposed method does not require knowledge of the junction's microscopic geometry, material information, defect location, or melting temperature.
T. Li et al., "System-Level Modeling for Transient Electrostatic Discharge Simulation," IEEE Transactions on Electromagnetic Compatibility, vol. 57, no. 6, pp. 1208 - 1308, Institute of Electrical and Electronics Engineers (IEEE), Dec 2015.
The definitive version is available at https://doi.org/10.1109/TEMC.2015.2443844
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Electrostatic discharge; Electrostatics; Defect location; Material information; System modeling; System-level modeling; Thermal runaways; Time dependent; Time integrals; Transient simulation models; Electrostatic devices; Common mode; electromagnetic compatibility (EMC); human machine model (HMM); IEC 61000-4-2; system efficient ESD design (SEED); transmission line pulser (TLP)
International Standard Serial Number (ISSN)
Article - Journal
© 2015 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Dec 2015