TLP IV Characterization of a 40 Nm CMOS IO Protection Concept in the Powered State
Abstract
In this paper, the interaction between the ESD protection concept and a powered output driver in a 40 nm CMOS process are investigated and characterized by TLP. By using IO test chips designed for HBM and CDM validation, the IV behavior of the pin is measured with the driver placed into various states.
Recommended Citation
B. Orr et al., "TLP IV Characterization of a 40 Nm CMOS IO Protection Concept in the Powered State," Proceedings of the 38th Electrical Overstress/Electrostatic Discharge Symposium (2016, Garden Grove (Anaheim), CA), vol. 2016-October, ESD Association, Oct 2016.
The definitive version is available at https://doi.org/10.1109/EOSESD.2016.7592566
Meeting Name
38th Electrical Overstress/Electrostatic Discharge Symposium (2016: Sep. 11-16, Garden Grove (Anaheim), CA)
Department(s)
Electrical and Computer Engineering
Research Center/Lab(s)
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
CMOS processs; ESD protection; I-V behavior; IV characterization; nocv2; Output drivers; Protection concepts; Test chips; CMOS integrated circuits
International Standard Book Number (ISBN)
978-158537289-8
International Standard Serial Number (ISSN)
0739-5159
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2016 ESD Association, All rights reserved.
Publication Date
01 Oct 2016
