Design of On-Chip Linear Voltage Regulator Module and Measurement of Power Distribution Network Noise Fluctuation at High-Speed Output Buffer
By applying on-chip linear VRM, PDN inductance is greatly decreased and PDN resonance peak disappears, which is usually generated by PCB/PKG inductance and on-chip capacitance. To confirm, we design an application circuits which have on-chip linear voltage regulator module (VRM) with aggressor and victim buffer. We validate the advantages of on-chip linear VRM by measuring fabricated chip in this research. Moreover, we show PDN self-impedance at output buffer by simulation with designed PCB's S-parameter, and eye-diagram power fluctuation up to 1 Gbps.
M. Lee et al., "Design of On-Chip Linear Voltage Regulator Module and Measurement of Power Distribution Network Noise Fluctuation at High-Speed Output Buffer," Proceedings of the 24th IEEE Conference on Electrical Performance of Electronic Packaging and Systems (2015, San Jose, CA), pp. 3-6, Institute of Electrical and Electronics Engineers (IEEE), Oct 2015.
The definitive version is available at https://doi.org/10.1109/EPEPS.2015.7347117
24th IEEE Conference on Electrical Performance of Electronic Packaging and Systems (2015: Oct. 25-28, San Jose, CA)
Electrical and Computer Engineering
Center for High Performance Computing Research
Second Research Center/Lab
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Capacitance; Electric network analysis; Electronics packaging; Inductance; Organic pollutants; Polychlorinated biphenyls; Scattering parameters; Voltage regulators; Application circuits; Eye diagrams; Linear voltage regulators; On-chip capacitance; On-chip voltage regulator; Power distribution network; Power fluctuations; Power integrity; Chip scale packages
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Article - Conference proceedings
© 2015 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Oct 2015