Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs


The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on RC transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range.


Electrical and Computer Engineering

Research Center/Lab(s)

Center for High Performance Computing Research

Second Research Center/Lab

Electromagnetic Compatibility (EMC) Laboratory


This work was supported in part by the National Science Foundation within the Division of Industrial Innovation and Partnerships under Grant IIP-1440110 and in part by Cisco Systems under Grant CG 586930.

Keywords and Phrases

Capacitance; Electric network analysis; Electric power distribution; Electronics packaging; Integrated circuit interconnects; Integrated circuit manufacture; Interfaces (materials); Inversion layers; Silicon; Threshold voltage; 3-D ICs; Conventional structures; Frequency characteristic; Power distribution network; RC transmission lines; Through-Silicon-Via; Through-Silicon-Via (TSV); Wide frequency range; Three dimensional integrated circuits; Enhanced TSV capacitance

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Article - Journal

Document Version


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© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Apr 2016