As design and test complexities of SoCs ever intensify, the balanced utilization of combined built-in self-test (BIST) and automated test equipment (ATE) testing becomes desirable to meet the required minimum-fault-coverage while maintaining an acceptable cost overhead. The cost associated with combined BIST/ATE testing of such systems mainly consists of 1) the cost induced by the BIST area overhead and 2) the cost induced by the overall testing time. In general, BIST is significantly faster than ATE, while it can provide only limited fault-coverage, and driving higher fault-coverage from BIST means additional area cost overhead. On the other hand, higher fault-coverage can be easily achieved from ATE, but excessive use of ATE results in additional test time. This paper proposes a novel probabilistic method to balance the fault-coverage and the test overhead costs in a combined BIST/ATE test environment. The proposed technique is then applied to two BIST/ATE test scenarios to find the optimal fault-coverage/cost combinations.

Meeting Name

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2004: Oct. 10-13, Cannes, France)


Electrical and Computer Engineering

Keywords and Phrases

BIST Area Overhead; SoC; Automated Test Equipment; Automatic Test Equipment; Built-In Self-Test; Combined BIST/ATE Test Environment; Fault Coverage/Test Cost Probabilistic Balancing; Fault-Coverage/Cost Combination Optimization; Integrated Circuit Testing; Optimisation; Probability; System-On-Chip; Testing Cost Overhead; Testing Time Cost

International Standard Book Number (ISBN)


International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2004 IEEE Computer Society, All rights reserved.

Publication Date

01 Oct 2004