High clock frequencies and short-edge rates in present high-speed digital systems result in EMI problems at increasingly higher frequencies. At these speeds, clock harmonics have sufficient energy in the range above 500 MHz to excite cavity modes of a conducting enclosure, and to drive even small length slots and apertures that are unavoidable in a practical design, and can result in an EMI problem. One approach to mitigate these problems is to partition the enclosure into several smaller internal shielded compartments. To study the factors which affect this partitioning, a special enclosure that can be divided into two internal compartments using center planes with different types of openings, was designed. The objective is to study the coupling through the center plane for different types and numbers of openings in the center plane and front panel. The experimental results are compared with finite-difference time-domain (FDTD) simulations.

Meeting Name

IEEE International Symposium on Electromagnetic Compatibility (1997: Aug. 18-22, Austin, TX)


Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

EMI Control; EMI Problems; FDTD Simulations; Cavity Modes Excitation; Center Plane Openings; Clock Harmonics; Digital Systems; Electromagnetic Compatibility; Electromagnetic Interference; Finite Difference Time-Domain Analysis; Finite-Difference Time-Domain; High Clock Frequencies; High-Speed Digital Systems; Internal Partitioning; Internal Shielded Compartments; Metallic Enclosures; Shielding; Short-Edge Rates

International Standard Book Number (ISBN)


International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 1997 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 1997