Abstract
Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize the FPGA's fixed resources is an efficient placement and routing mechanism. This paper presents particle swarm optimization (PSO) for FPGA placement and routing. Preliminary results for the implementation of an arithmetic logic unit on a Xilinx FPGA show that PSO is a potential technique for solving the placement and routing problem.
Recommended Citation
G. K. Venayagamoorthy and V. G. Gudise, "FPGA Placement and Routing Using Particle Swarm Optimization," Proceedings of the IEEE Computer society Annual Symposium on VLSI, 2004, Institute of Electrical and Electronics Engineers (IEEE), Jan 2004.
The definitive version is available at https://doi.org/10.1109/ISVLSI.2004.1339567
Meeting Name
IEEE Computer society Annual Symposium on VLSI, 2004
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
FPGA; PSO; Xilinx; Arithmetic Logic Unit; Digital Circuits; Field Programmable Gate Arrays; Fixed Resources; Network Routing; Optimisation; Particle Swarm Optimization; Placement Mechanism; Routing Mechanism
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jan 2004
