This paper addresses the issues of field programmable gate arrays (FPGA) reconfigurable memory systems with faulty physical memory cells and proposes yield measurement techniques. Static yield (i.e., the yield which does not take into account the inherited redundancy utilization for repair) and dynamic yield (i.e., the yield which takes into account the inherited redundancy utilization for repair) of FPGA reconfigurable memory systems and their characteristics are extensively analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate numerous target memory configurations, and redundant memory cells, if any, can be used as spares to enhance the dynamic yield of a target memory configuration. Three fundamental strategies are introduced and analyzed; i.e., redundant bit utilization, redundant word utilization, and a combination of both. Mathematical analysis of those techniques also has been conducted to study their effects on the yield. Selecting the most yield enhancing logical memory configuration which can accommodate a target memory requirement among the candidate configurations is referred to as optimal fitting. Optimal fitting algorithms for single configuration fitting, sequential reconfiguration system fitting, and concurrent reconfiguration system fitting are investigated based on the proposed yield analysis techniques.
M. Choi and N. Park, "Dynamic Yield Analysis and Enhancement of FPGA Reconfigurable Memory Systems," IEEE Transactions on Instrumentation and Measurement, vol. 51, no. 6, pp. 1300-1311, Institute of Electrical and Electronics Engineers (IEEE), Dec 2002.
The definitive version is available at https://doi.org/10.1109/TIM.2002.808046
Electrical and Computer Engineering
Keywords and Phrases
FPGA Reconfigurable Memory Systems; Concurrent Reconfiguration System Fitting; Dynamic Yield Analysis; Embedded Reconfiguration Memory System; Fault Tolerant Computing; Faulty Physical Memory Cells; Field Programmable Gate Arrays (FPGA); Integrated Circuit Measurement; Integrated Circuit Reliability; Integrated Circuit Yield; Integrated Memory Circuits; Mathematical Analysis; Optimal Fitting Algorithms; Randomly Distributed Memory Cell Faults; Redundancy; Redundant Bit Utilization; Redundant Memory Cells; Redundant Word Utilization; Sequential Reconfiguration System Fitting; Single Configuration Fitting; Static Yield; Yield Enhancement; Yield Measurement Techniques; Concurrent Reconfiguration; Dynamic Yield; FPGA-Based Instrumentation; Memory Yield Enhancement; Memory Yield Measurement; Optimal Fitting; Reconfigurable Memory; Sequential Reconfiguration
International Standard Serial Number (ISSN)
Article - Journal
© 2002 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Dec 2002