This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NULL convention logic (NCL) Library. The proposed design uses three static LUT's for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and operation mode. The static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process.
W. K. Al-Assadi et al., "Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Static NCL," Proceedings of the IEEE Region 5 Conference, 2008, Institute of Electrical and Electronics Engineers (IEEE), Apr 2008.
The definitive version is available at https://doi.org/10.1109/TPSD.2008.4562766
IEEE Region 5 Conference, 2008
Electrical and Computer Engineering
National Science Foundation (U.S.)
Keywords and Phrases
CMOS Logic Circuits; Field Programmable Gate Arrays; Logic Design; Logic Gates; Table Lookup
Article - Conference proceedings
© 2008 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Apr 2008